1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory formed on a semiconductor chip and having a plurality of sense amplifiers, such as a bit-line sense amplifier, which are connected to the reference potential terminal of the semiconductor chip by means of a common line.
2. Description of the Related Art
FIG. 3 is a circuit diagram showing a part of the conventional DRAM (Dynamic Random Access Memory). As is shown in this figure, the DRAM has bit-line sense amplifiers SAa SAb, ..., each connected to a different pair of bit lines, (BLa, BLa), (BLb, BLb), or the like. These bit-line sense amplifiers are connected to the reference potential (Vss) terminal (i.e., the Vss potential pad) by means of a common source line 31 and a MOS transistor 32. (The MOS transistor 32 is used to activate the sense amplifiers SAa, SAb, .... Each sense amplifier comprises two N-type MOS transistors, whose drains and gates are cross-coupled, and whose sources are connected to each other and also to the common source line 31.
The current flowing in that MOS transistor of each sense amplifier, which is used to reduce the potential of the bit lines to a low level, is supplied through the source line 31 and discharged at the Vss terminal. Various parasitic resistances exist between the sense amplifiers and the Vss terminal, such as the resistance of the source line 31, the resistance of the MOS transistor 32, and the resistance of the Vss power-supply line. The greater the storage capacity of the DRAM, and hence, the larger the chip of the DRAM, the higher these parasitic resistances. Further, the greater the storage capacity of the DRAM, the greater the number of the bit-line sense amplifiers, which are simultaneously activated. More specifically, when the storage capacity increases four times, twice as many bit-line sense amplifiers are activated at the same time in order to accomplish refresh operation.
Consequently, the CR time constant of the sense amplifiers increases in proportion to the storage capacity of the DRAM. This is because the CR time constant is the product of capacitance C and resistance R, where C in turn is the product of the capacitance of one bit line and the number of the sense amplifiers, and R is the sum of the parasitic resistances existing between each sense amplifier and the Vss terminal.
No data can be read from a bit line to an I/0 bus until the sense amplifiers amplify the potentials of the bit lines to a sufficient degree. (Were the data be read out before the sense amplifiers sufficiently amplify the potentials of the bit lines, it would be destroyed) An increase of the CR time constant of the sense amplifiers directly results in an increase of the access time of the DRAM. In other words, the source potential of each sense amplifier cannot go fast to the Vss potential despite the amplification of the bit-line potential, and the bit lines cannot be latched quickly.
Two methods of decreasing the CR time constant have been proposed. The first method is to reduce the capacitance of each bit line. To this end, the memory cells are divided into more blocks, so that less memory cells are connected to one bit line. When the memory cells are divided into many blocks, however, the DRAM needs to have more decoders and more sense amplifiers, which occupy a greater area on the semiconductor chip. The second method is to use a source line comprising two aluminum layers, thereby reducing the parasitic resistance existing between each sense amplifier and the Vss terminal. This method is a forced, fast driving of the large capacitance of the source line, and results in capacitive coupling. This capacitive coupling is likely to greatly change the substrate capacitance, and to influence the other circuits which are used in combination within the DRAM adversely.